D Matrix

Power Performance Architect, Senior Staff - Accelerator Design

Systems Hardware Engineer, Principal

Principal Software ML Test Engineer

Post-Silicon Validation Engineer, Staff

Emulation Engineer, Senior (L3) (26-43)

Analog Design Engineer Senior, Staff, Senior Staff (L3/L4/L5)

Principal Software Engineer - SDK & Lowering Stack

Principal Architect, Performance Analysis and Modeling

AI Security Architect, Principal

HW Design Verification Intern

Machine Learning Intern - Dynamic KV-Cache Modeling for Efficient LLM Inference

Digital Design Engineer, Micro-Architect, Principal

FPGA Design Engineer, Senior Staff

Analog IC Design Intern

Sr. Dir, Customer Platform Engineering

HW Engineering Intern - PCB Layout Automation & AI Tooling

Software Engineering Intern, Simulation and Modeling

Machine Learning Research Intern

Runtime Engineering Intern

Principal AI/ML System Software Engineer

Software Engineer, Staff - SIMD Kernels

Senior Runtime Systems Engineer

Software Engineer, Developer and Qualification Tools

Software Engineer, Staff - Kernels

Sr, Staff Technical Program Manager-SW

Technical Program Manager – Software/Release, Principal

Technical Program Manager – Hardware/Silicon, Principal

Technical Program Manager - Hardware/Systems, Principal

Senior Staff AI/ML System Software Engineer

Thermal Engineer - Contract

Software Infrastructure Engineer, Senior Staff

Micro-Architect / RTL Design - CPU, Principal

Analog Design Engineer, Staff

Design Verification Engineer, (L3/L4/L5/)